What are ECC DRAMs?

ECC DRAM is a special product line developed for the companies who have high concern about reliability and functionality in rigorous environments.

ECC DRAMs are memory components with integrated error correction logic. The ECC DRAMs internally generate parity-data for each data-block of 64b, which allows them to detect and correct single bit errors within each of he 64b internal data-blocks. As an example, a 1Gb ECC DRAM internally consists of 16 million blocks of 64b.

Even in the extremely rare cases, where each and every block would have a single bit error, the DRAM would still work perfectly due to the ECC algorithm correcting all these errors. The error correction algorithm is identical to what is used on server memory modules, but servers perform this algorithm via the CPU, while the ECC DRAMs perform the algorithm in the DRAM chip itself. This is why ECC DRAMs make it possible to add a "server-level of memory reliability" to any application, even if the CPU on your application is unable to perform error correction.

How often do ECC correctable single bit errors occur?  What about double and multi-bit errors?

The fact is, DRAM components are not perfect. Some databits inside every DRAM will flip from 0 to 1 or from 1 to 0 from time to time. There are multiple analyses and statistics about how often bit flips in DRAMs occur, but none of them can be used universally for all applications. One interesting research comes from the University of Toronto, which is called 'DRAM Errors in the Wild - A Large-Scale Field Study'. This study monitored the DRAM errors in the thousands of systems of the famous Google server farm for a period of two and a half years. All those servers were surely perfectly air conditioned, dust free and protected from radiations of all kinds. Still they came to the result of 25,000 to 70,000 FIT (failures per billion device hours) of 'ECC correctable errors' per Mb of DRAM. This converts into an average of one single bit error every 14 to 40 hours per Gb of DRAM.

The field study also explains that the error rate increases with the age of the memory. Brand new DRAMs might not show any errors for weeks or months, but then the error rate may rather suddenly go up.

Uncorrectable errors could be double or multi-bit errors, or even complete functional fails from the DRAM. These cannot all be corrected, but are extremely rare.

A 1Gb ECC DRAM contains 16 million blocks of 64b datawords. Per each of these 64b words, one error is correctable. In other words: Statistically, one out of 16 million hits might be a double bit error. If one error hits per day, this would mean that it takes hypothetically 16 Million days or 48,000 years for a double bit error to hit. But this is just the maths. In the end, the real numbers depend on the stress and the environment the application is running in.

Why should I use ECC DRAM in my application, even if I have almost no field returns or known issues?

DRAM errors are transient; they come and go. For example, think about the electronics in your household, or the random blue screen on your computer; the navigation system sometimes suddenly hangs or shows unusual icons on the screen; the WiFi router does not want to connect to the internet from time to time, or repeatedly asks you for your password (even though you have aleady entered it correctly 10 times!).  After a reset or reboot, these applications work fine again.  In most cases a "single event effect", like a DRAM single-bit-error, was the root cause.  Do you then return your device to the manufacturer simply because you had a non-repeatable problem which was solved after a simple reset or reboot?  The answer is likely, no.  Nonetheless, it's still a nuisance.

With all that said, not every error results in a system crash. If the error hits graphics, audio data, or unused DRAM areas, the user typically does not even notice it. When the error hits important data, calculations, or the program functions might be corrupted. The worst scenario is a hit in the program code.

Real defects in DRAM components are extremely rare. The majority of problems are single event effects which customers will normally not see repeated again.

On a server, for example, the customers expect them to run 24/7, 365 days a year. This is why server CPUs are equipped with an ECC logic and require special 72b wide memory modules that can store 8 parity bits in addition to the 64Db for every access.

It's best to use error correction if your product is to be running stable, even after months and years of use, and especially when exposed to other devices or changable environments, like cell phones or the sun, so as to avoid disturbances or major temperature fluctuations.

For which applications should I use ECC DRAM?

It depends on the reliability you expect from your application. You decide if you can accept the risk of data corruption, malfunction or crashes to happen within your application or not.

Today's conventional DRAMs used in simple gaming computers are identical to the DRAMs used in high-end industrial applications; same part numbers, same products. For automotive applications the DRAM manufacturers perform a more extensive test process, but even those 'AEC-Q100' qualified DRAMs still have no protection from disturbing external influences, they can degrade, react sensitively to line-noise, etc.

Stronger quality testing is not a guarantee to have no single bit errors.

Are ECC DRAMs compatible with conventional DRAMs?

Yes, they are 100% fit, form, and functionally compatible with conventional DRAMs according to JEDEC specifications. They will work as drop-in-replacements (pin-topin compatible) without any changes to your hardware or software. Also there is no time difference compared to conventional DRAM. The error correction logic of the ECC DRAMs is extremely fast, thus there are no additional delays or latencies compared to the JEDEC standard specifications.

What is the root cause for these single-bit-errors?

There are many root causes. A major factor is that the memory cells in the DRAM have slight weaknesses and cause a bit flip. However, even those weak cells are not permanently damaged. The cell might work fine for a million or more accesses and then suddenly lose its data in one moment which is then not repeatable. You can only find out if it is a weakness by checking if that same databit cell is affected again by an error after some time.

DRAMs also suffer from aging; they degrade. The isolations of some single bit cells get weaker and the leakage increases. Single bit errors arbitrarily appear although there has been no sign of problems in the past. Radiation of any kind can also influence the DRAM cells. Even the natural ambient radiation we have on earth is able to flip a bit in a DRAM. The higher above sea level, the stronger the radiation. Also antennas from cell phones, for example, can disturb the memory cells of a DRAM directly.

Heat is a major issue for memory components. As a DRAM stores the data in little capacitors, which have a certain leakage anyway, higher temperatures cause an increase in leakage and at some point the first one or two memory cells will lose their data before they get refreshed by the CPU. This is called a 'retention fail'.

Running DRAMs constantly under high temperatures or exposed to radiation accelerates the degradation of the products.

Can I upgrade existing applications with ECC DRAM?

Yes, absolutely. If you assemble your board with ECC DRAMs instead of using conventional DRAMs, you will immediately have the error correction functionality.

Can Intelligent Memory provide memory modules built with ECC DRAM?

ECC DRAMs are pin-to-pin compatible with conventional DRAMs, thus they can also be put onto any memory module PCB, boosting these modules' unparalleled reliability. Any application taking DIMMs, SODIMMs, Mini DIMMs or other form factors can take advantage of the ECC protection, no matter if the CPU supports ECC or not. Memory modules typically are 64 or 72b wide and are made of multiple DRAMs (with x4 or x8 bit-width) running in parallel. Since every single ECC DRAM performs its own error correction algorithm, a module built with ECC DRAMs can perform multiple data verifications & corrections in parallel. Even 72b wide modules used on applications that perform ECC via the CPU would be able to add multiple levels of reliability.

Any memory module manufacturing company can build modules based on ECC DRAMs. Depending on the reliability you expect or require from your application, you can decide if you are able to accept the risk of data corruption, malfunction or crashes to occur.

Today's conventional DRAMs used in simple gaming computers are identical to the DRAMs used in high-end industrial applications. Same part numbers, same products. For automotive applications the DRAM manufacturers perform more extensive test processes, but even those 'AEC-Q100' qualified DRAMs still have no protection from disturbing external factors, degredation, sensitivity to line noise, etc. In conclusion, higher or stronger quality testing does not necessarily guarantee to have no single-bit errors.

How effective is the ECC error correction in the ECC DRAMs?

The answer to this depends on your CPU bus' width and the DRAM's bit-width, because every single ECC DRAM IC will perform its individual error-correction. For example, if your CPU has a 64b wide memory bus and you use 8 ECC DRAM components in a x8 organization, you will have a total of 8 error corrections running in parallel. This way even multiple single-bit errors within the 64Db will be correctable (one per component).

Let's compare this to the error correction as it is done on servers and other applications by the CPU:

If the CPU is ECC capable, it typically has a 72b wide memory bus. Nine DRAM components in a x8 configuration, or 18 DRAM components in a x4 organization, have to run in parallel. However, of the overall total 72Db, only one bit can be corrected by the CPU-internal ECC.

Therefore in conclusion, in the majority of applications, multiple DRAMs are in parallel connected to the memory bus of the CPU. Using ECC DRAMs is much more effective than the CPU-controlled ECC due to the fact that every single ECC DRAM can perform an individual error-correct, which multiplies the effectiveness.

As a side note, it would even be possible to use ECC DRAMs together with an ECC-capable CPU. This way each ECC DRAM performs a correction and the CPU will do another final check and correction of the data.

What is Flash Memory?

Flash Memory is a non volatile electronically erasable and programmable type of semiconductor memory.

What is MLC Flash?

MLC stand for Multi Level Cell. In an MLC, 2Db are keept in one Flash cell. Two databits require 4 voltage levels to be maintained in one cell which are detected by comparators. The advantage is a higher bit density but at the expense of smaller voltage margins in comparison to Single Level Cells (SLC) where only two voltage levels need to be detected: charged or not charged.

What is TBW?

TBW (Terabytes Written) is a measurement of the SSD's expected lifespan, which represents the amount of data written to the device.

What does SATA mean?

A Serial Advanced Technology Attachment (SATA) Bus is a serial interface widely used to connect hard disk or similar Flash-based storages (SSDs) to the main control unit, such as a PC motherboard.

What does SSD mean?

SSD stands for Solid State Disk, which means a storage device being based on solid state (or semiconductor), typically Flash-based, memory. There is actually no physical disk used as in mechanical hard disk drives (HDDs) which have rotating disks storing the data in magnetic particles. An SSD stores the data in raw Flash components, managed by a Flash controller which communicates to the main units (motherboard) through an interface like SATA, PCIe, etc.

What does Raw NAND stand for?

RAW NAND comes without an error collection mechanism, nor cell lifetime management.  It requires an external host controller to perform the management of previous functions.

What is NAND Flash?

A type of non-volatile storage technology that does not require power to retain data is NAND flash memory. NAND Flash is organised in blocks. It is typically in use with applications where bigger data quantities have to be written and read in a much quicker manner.

What does Managed NAND stand for?

Managed NAND, like eMMC and SPI NAND, contains a built-in controller module, and by design it can handle the ECC requirements of the Raw NAND. Firmware handling the ECC strategies (performing retry, block bad identification, and replacement) is built into the memory media, which must be provided in the software layer for Raw Flash.

What is pSLC?

pSLC stands for pseudo-SLC.  Pseudo Single-Level Cell (pSLC) is one of the technologies which uses Multi-Level cell (MLC) or Triple-Level cell (TLC) NAND Flash so as to reduce the number of bits which are stored in each cell down to one. The pSLC configuration on muliti-level cell (MLC, TLC) NAND only takes 2b for data storage from original 4b MLC or 8b TLC NAND. It can dramatically increase the reliability and endurance of NAND Flash. It supports the SSDs in maintaining high P/E cycles, high TBW demand in industrial and embedded applications, and also increases data access performance.

What is Data Retention?

Data Retention is the ability to retain stored information over time. The Data Retention Time (DRT) is the period of time the memory can retain data in an unbiased condition. Data retention time is also a function of P/E cycles and temperature. With that said, NAND Flash endurance and TBW highly depend on the data retention period required.

What is eMMC?

eMMC (embedded Multimedia Card) is "managed Flash".  Managed Flash is when media (i.e. Flash controller) and raw flash memory are combined in one common BGA Package. The raw Flash management is handled by the Flash controller thus the eMMC user does not need to worry about poor block management, ECC, wear leveling, etc.